UNAI BIDARTE PERAITA-rekin lankidetzan egindako argitalpenak (9)

2018

  1. SEU emulation in industrial SoCs combining microprocessor and FPGA

    Reliability Engineering and System Safety, Vol. 170, pp. 53-63

2017

  1. Estimating the SEU failure rate of designs implemented in FPGAs in presence of MCUs

    Microelectronics Reliability, Vol. 78, pp. 85-92

2016

  1. Effect of different design stages on the SEU failure rate of FPGA systems

    2016 Conference on Design of Circuits and Integrated Systems, DCIS 2016 - Proceedings

  2. Synchronization of faulty processors in coarse-grained TMR protected partially reconfigurable FPGA designs

    Reliability Engineering and System Safety, Vol. 151, pp. 1-9

2015

  1. Dependability in FPGAs, a Review

    2015 Conference on Design of Circuits and Integrated Systems, DCIS 2015

2014

  1. A Versatile FPGA Demonstration Platform for Academic Use

    Libro de actas del XI Congreso de tecnologías, aprendizaje y enseñanza de la electrónica, TAEE 2014: 11,12 y 13 de Junio de 2014. Universidad de Deusto. Bilbao

  2. A versatile FPGA demonstration platform for academic use

    Proceedings of XI Tecnologias Aplicadas a la Ensenanza de la Electronica (Technologies Applied to Electronics Teaching), TAEE 2014

2013

  1. Fast context reloading lockstep approach for SEUs mitigation in a FPGA soft core processor

    IECON Proceedings (Industrial Electronics Conference)

2012

  1. Interface tasks oriented 8-bit soft-core processor

    9th FPGAworld Conference - Academic Proceedings 2012, FPGAworld 2012