JAGOBA
ARIAS PEREZ
Researcher in the period 2001-2007
Publications (34) JAGOBA ARIAS PEREZ publications
2010
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Neuro semantic thresholding using OCR software for high precision OCR applications
Image and Vision Computing, Vol. 28, Núm. 4, pp. 571-578
2008
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LL-MAC: A low latency MAC protocol for wireless self-organised networks
Microprocessors and Microsystems, Vol. 32, Núm. 4, pp. 197-209
2007
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Decompression dual core for SoPC applications in high speed FPGA
IECON Proceedings (Industrial Electronics Conference)
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Energy aware medium access control protocols
Wireless Communications Research Trends (Nova Science Publishers, Inc.), pp. 123-163
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GPS-less location algorithm for wireless sensor networks
Computer Communications, Vol. 30, Núm. 14-15, pp. 2904-2916
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Hardware architecture for a general regression neural network coprocessor
Neurocomputing, Vol. 71, Núm. 1-3, pp. 78-87
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High-precision DRM demodulator for remote monitoring
IECON Proceedings (Industrial Electronics Conference)
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OSCRYB: Open source CRYpto-bridge for secure ethernet point-to-point industrial communications
IECON Proceedings (Industrial Electronics Conference)
2006
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A design methodology for progressive families of devices
WSEAS Transactions on Electronics, Vol. 3, Núm. 9, pp. 499-504
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Architecture of a real-time wavelet transform calculation SoPC core for industrial applications
IECON Proceedings (Industrial Electronics Conference)
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Comparison of two designs for the multifunction vehicle bus
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Modifying slots in test vectors to validate decoders of a train network
Second International Conference on Wireless and Mobile Communications, ICWMC 2006
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Node synchronization in wireless sensor networks
Second International Conference on Wireless and Mobile Communications, ICWMC 2006
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Run-time reconfigurable hardware-software architecture for PID motor control IP cores
IECON Proceedings (Industrial Electronics Conference)
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SOM Segmentation of gray scale images for optical recognition
Pattern Recognition Letters, Vol. 27, Núm. 16, pp. 1991-1997
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Simulink/modelsim simulable VHDL PID core for industrial SoPC multiaxis controllers
IECON Proceedings (Industrial Electronics Conference)
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Topics on power aware design
WSEAS Transactions on Communications, Vol. 5, Núm. 2, pp. 327-334
2005
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A tiny microprocessor floating point implementation of a general regression neural network
WSEAS Transactions on Computers, Vol. 4, Núm. 2, pp. 280-285
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Implementation of a modified Fuzzy C-Means clustering algorithm for real-time applications
Microprocessors and Microsystems, Vol. 29, Núm. 8-9, pp. 375-380
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Multiprocessor SoPC-core for FAT volume computation
Microprocessors and Microsystems, Vol. 29, Núm. 10, pp. 421-434