JAGOBA
ARIAS PEREZ
Researcher in the period 2001-2007
UNAI
BIDARTE PERAITA
PROFESORADO AGREGADO
Publications by the researcher in collaboration with UNAI BIDARTE PERAITA (12)
2007
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Decompression dual core for SoPC applications in high speed FPGA
IECON Proceedings (Industrial Electronics Conference)
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Hardware architecture for a general regression neural network coprocessor
Neurocomputing, Vol. 71, Núm. 1-3, pp. 78-87
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OSCRYB: Open source CRYpto-bridge for secure ethernet point-to-point industrial communications
IECON Proceedings (Industrial Electronics Conference)
2006
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Architecture of a real-time wavelet transform calculation SoPC core for industrial applications
IECON Proceedings (Industrial Electronics Conference)
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Comparison of two designs for the multifunction vehicle bus
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Run-time reconfigurable hardware-software architecture for PID motor control IP cores
IECON Proceedings (Industrial Electronics Conference)
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Simulink/modelsim simulable VHDL PID core for industrial SoPC multiaxis controllers
IECON Proceedings (Industrial Electronics Conference)
2005
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A tiny microprocessor floating point implementation of a general regression neural network
WSEAS Transactions on Computers, Vol. 4, Núm. 2, pp. 280-285
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Multiprocessor SoPC-core for FAT volume computation
Microprocessors and Microsystems, Vol. 29, Núm. 10, pp. 421-434
2004
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Co-simulation virtual platform for reconfigurable multiprocessor hybrid cores development
Proceedings of the International Conference on Modeling, Simulation and Visualization Methods, MSV'04 and Proceedings of the Int. Conference on Algorithmic Mathematics and Comput. Sci., AMCS'04
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High throughput serpent encryption implementation
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
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Run-time reconfigurable hybrid multiprocessor cores
Proceedings of the IEEE International Conference on Industrial Technology