Publikationen, an denen er mitarbeitet JAIME JIMENEZ VERDE (4)

2018

  1. SEU emulation in industrial SoCs combining microprocessor and FPGA

    Reliability Engineering and System Safety, Vol. 170, pp. 53-63

2016

  1. Effect of different design stages on the SEU failure rate of FPGA systems

    2016 Conference on Design of Circuits and Integrated Systems, DCIS 2016 - Proceedings

2013

  1. Fast context reloading lockstep approach for SEUs mitigation in a FPGA soft core processor

    IECON Proceedings (Industrial Electronics Conference)

2012

  1. Interface tasks oriented 8-bit soft-core processor

    9th FPGAworld Conference - Academic Proceedings 2012, FPGAworld 2012