Publications dans lesquelles il/elle collabore avec Víctor Viñals Yufera (10)

2020

  1. Reducing the WCET and analysis time of systems with simple lockable instruction caches

    PLoS ONE, Vol. 15, Núm. 3

2019

  1. Tasa de aciertos ideal y predecible para la transposición de matrices en caches de datos

    Avances en Arquitectura y Tecnología de Computadores: Actas de Jornadas SARTECO, Cáceres, 18 a 20 de septiembre de 2019| (Servicio de Publicaciones), pp. 172-181

2016

  1. Obtención del WCET óptimo con caches de instrucciones bloqueables (Lock-MS) en Otawa

    V Simposio de Sistemas de Tiempo Real (Ediciones Universidad de Salamanca), pp. 95-106

2015

  1. A predictable hardware to exploit temporal reuse in real-time and embedded systems

    Journal of Systems Architecture, Vol. 61, Núm. 5-6, pp. 227-238

  2. ACDC: Small, predictable and high-performance data cache

    ACM Transactions on Embedded Computing Systems, Vol. 14, Núm. 2, pp. 38

2013

  1. Optimizing a combined WCET-WCEC problem in instruction fetching for real-time systems

    Journal of Systems Architecture, Vol. 59, Núm. 9, pp. 667-678

2012

  1. A small and effective data cache for real-time multitasking systems

    Real-Time Technology and Applications - Proceedings

2011

  1. Improving the WCET computation in the presence of a lockable instruction cache in multitasking real-time systems

    Journal of Systems Architecture, Vol. 57, Núm. 7, pp. 695-706

2010

  1. Combining prefetch with instruction cache locking in multitasking real-time systems

    Proceedings - 16th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2010

2008

  1. Avoiding the WCET overestimation on LRU instruction cache

    Proceedings - 14th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2008